A 54mw 1.2 gs/s 71.5 db sndr 50mhz bw vco-based ct δσ adc using dual phase/frequency feedback in 65nm cmos K Reddy, S Dey, S Rao, B Young, P Prabha, PK Hanumolu
VLSI Circuits (VLSI Circuits), 2015 Symposium on, C256-C257, 2015
50 2015 A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique H Maghami, P Payandehnia, H Mirzaie, R Zanbaghi, H Zareie, J Goins, ...
IEEE Journal of Solid-State Circuits, 2019
35 2019 A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3 P Payandehnia, H Maghami, H Mirzaie, M Kareppagoudr, S Dey, ...
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018
35 2018 A 50 MHz BW 76.1 dB DR two-stage continuous-time delta–sigma modulator with VCO quantizer nonlinearity cancellation S Dey, K Reddy, K Mayaram, TS Fiez
IEEE Journal of Solid-State Circuits 53 (3), 799-813, 2017
34 2017 A Highly Linear OTA-Free VCO-Based 1-1 MASH H Maghami, P Payandehnia, H Mirzaie, R Zanbaghi, S Dey, K Mayaram, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (7), 2440-2453, 2019
27 2019 350 mV, 5 GHz class-D enhanced swing differential and quadrature VCOs in 65 nm CMOS AG Roy, S Dey, JB Goins, TS Fiez, K Mayaram
IEEE Journal of Solid-State Circuits 50 (8), 1833-1847, 2015
23 2015 A Hybrid Continuous-Time Incremental and SAR Two-Step ADC With 90.5-dB DR Over 1-MHz BW Y Wang, S Dey, T He, L Shi, J Zheng, M Kareppagoudr, Y Zhang, ...
IEEE Solid-State Circuits Letters 5, 122-125, 2022
11 2022 A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ modulator with 2nd order noise-shaping and pipelined SAR-VCO based quantizer S Dey, K Mayaram, T Fiez
2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019
8 2019 A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation S Dey, K Reddy, K Mayaram, T Fiez
2017 IEEE Custom Integrated Circuits Conference (CICC), 2017
6 2017 A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM AG Roy, S Dey, J Goins, K Mayaram, TS Fiez
Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the, 1-4, 2014
5 2014 0.9 V, 79.7 dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique H Maghami, P Payandehnia, H Mirzaie, R Zanbaghi, S Dey, J Goins, ...
2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019
4 2019 Multi-path analog system with multi-mode high-pass filter R Zanbaghi, S Dey, DJ Allen, JL Melanson, A Satoskar
US Patent 10,069,483, 2018
1 2018 Design Techniques for Wide-bandwidth Continuous-time Delta-sigma Modulators with Noise-shaping Quantizers S Dey
2018 A closed loop stability analysis for the Particle Swarm Optimization dynamics D Sen, S Dey
2007 IET-UK International Conference on Information and Communication …, 2007
2007 Stability analysis of the Ant System dynamics with non-uniform pheromone deposition rules D Sen, S Dey
2007 IET-UK International Conference on Information and Communication …, 2007
2007 
