| Intelligent Illumination System to Prevail over Possible Diseases due to over-and. under-illumination MJS Edle, AP Thakare, A Agarkar International Journal of Enterprise Computing and Business Systems Systems 1 …, 2011 | 9 | 2011 |
| Development of concurrent architecture of vedic multiplier PR Deshmukh, JS Edle 2018 Fourth International Conference on Computing Communication Control and …, 2018 | 2 | 2018 |
| Application specific architecture of 32-Bit Vedic multiplier JS Edle, PR Deshmukh 2017 International Conference on Computing, Communication, Control and …, 2017 | 1 | 2017 |
| Witricity: A Novel Concept of Power Transfer PJSE Miss. Bhagyashri D. Mokalkar, MIss. Chaitali B. Tale International Journal of Engineering Inventions 1 (7), 51-59, 2012 | 1* | 2012 |
| An Integration of Emotional Attire-the Artificial Intelligence SJ Wakharia, P Jitendra, SE Ms, DJ Wakharia Int. J. Eng. Res. Appl 2 (1), 497-502, 2012 | 1 | 2012 |
| Design and Development of Parallel Vedic Processing Architecture through ASIC Design Methodology DB Alaspure, SR Dixit, JS Edle International Journal of Intelligent Systems and Applications in Engineering …, 2024 | | 2024 |
| Concurrent Computation Strategies: Unveiling the Power of Vedic Mathematics DB Alaspure, SR Dixit, JS Edle International Journal of Intelligent Systems and Applications in Engineering …, 2024 | | 2024 |
| Vedic Mathematics: An Approach for Parallel Computing DB Alaspure, SR Dixit, JS Edle Design Engineering, 13314-13332, 2021 | | 2021 |
| Performance Analysis of Multifarious Programmable Gate Array Architecture for Vedic Multiplier JS Edle, PR Deshmukh 2017 International Conference on Computing, Communication, Control and …, 2017 | | 2017 |
| Device and Interface for Ternary Logic Using VLSI Tool PJSEDPR Deshmukh IN Patent App. 4359/MUM/2,015, 2017 | | 2017 |
| Intelligent Power Reduction Techniques for Indoor and Outdoor Applications PAPT Prof. Jitendra S. Edle IN Patent App. 3642/MUM/2,015, 2017 | | 2017 |
| VMFPGA: A dynamic approach for high speed computing JS Edle, PR Deshmukh 2016 International Conference on Computing Communication Control and …, 2016 | | 2016 |
| Concurrent Architecture of Vedic Multiplier-An Accelerator Scheme for High Speed Computing DPRD Prof. Jitendra S. Edle IN Patent App. 3315/MUM/2,015, 2015 | | 2015 |
| Advanced Automatic Luminance Management and Real Time Counting System Using High Computing Programmable Gate Arrays: One Step Towards Green IT A Department of Electronics and Telecommunication Engineering, SIPNA College ... International Journal of Latest Trends in Computing 2 (1), 147-151, 2011 | | 2011 |
| Development of Concurrent Architecture of Vedic Multiplier an Accelerator Scheme for High Speed Computing JS Edle Amravati, 0 | | |
Dr P R DeshmukhHead of Department ,Government College of Engineering, AmravatiVerified email at ieee.org
Dr P R DeshmukhHead of Department ,Government College of Engineering, AmravatiVerified email at ieee.org