| VHDL для проектирования вычислительных устройств М Сергиенко, Анатолий DiaSoft, 1-210, 2003 | 122 | 2003 |
| Implementation of Givens QR-Decomposition in FPGA A Sergyienko, O ·Maslennikov Parallel Processing and Applied Mathematics. LNCS 2328, 458-465, 2002 | 41 | 2002 |
| Parallel Implementation of Cholesky LLT-Algorithm in FPGA-Based Processor O Maslennikow, V ·Lepekha, A Sergyienko, A ·Tomas, R Wyrzykowski Lecture Notes in Computer Science 4967, 137-147, 2008 | 36 | 2008 |
| FPGA Implementation of the Conjugate Gradient Method O Maslennikow, V Lepekha, A ·Sergyienko Proceeding PPAM'05 Proceedings of the 6th international conference on …, 2006 | 23 | 2006 |
| Отображение периодических алгоритмов в программируемые логические интегральные схемы АМ Сергиенко, ВП Симоненко Электронное моделирование 29 (2), 49-61, 2007 | 18 | 2007 |
| Mapping DSP Algorithms into FPGA O Maslennikow, A Sergiyenko Parallel Computing in Electrical Engineering, 2006. PAR ELEC 2006 …, 2006 | 18 | 2006 |
| Отображение периодических алгоритмов в программируемые логические интегральные схемы АМ Сергиенко, ВП Симоненко Моделирование-2006. —14-16 мая 2006, Киев 2, 2006 | 18 | 2006 |
| Configurable microcontroller array O Maslennikov, J Shevtshenko, A Sergyienko Proceedings. International Conference on Parallel Computing in Electrical …, 2002 | 14 | 2002 |
| Алгоритмические модели обработки потоков данных АМ Сергиенко, ВП Симоненко Электронное моделирование 30 (6), 49-60, 2008 | 12 | 2008 |
| A Method for Synchronous Dataflow Retiming A Sergiyenko, A Serhienko, A Simonenko IEEE First Ukraine Conference on Electrical and Computer Engineering …, 2017 | 11 | 2017 |
| Implementation of Cholesky LLT-Decomposition Algorithm in FPGA-Based Rational Fraction Parallel Processor O Maslennikow, P ·Ratuszniak, A ·Sergyienko Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th …, 2007 | 11 | 2007 |
| Configurable Microprocessor Array for DSP Applications O Maslennikow, J Shevtshenko, A Sergyienko LNCS 3019, 2004 | 9 | 2004 |
| A method for the structural synthesis of pipelined array processors JS Kanevski, AM Sergyienko, H Piech Proc. of the 1-st Int. Conf. on Parallel Proc. and Appl. Math., PPAM, 100-109, 1994 | 8 | 1994 |
| FPGA Implementation of CORDIC Algorithms for Sine and Cosine Floating-Point Calculations A Sergiyenko, L Moroz, L Mychuda, V Samotyj The 11th IEEE International Conference on Intelligent Data Acquisition and …, 2021 | 7 | 2021 |
| Digital Filter Design using VHDL A Sergiyenko, A Serhienko 5-th International Conference "High Performance Computing" HPC-UA 2018 …, 2018 | 7 | 2018 |
| Микропроцессорные устройства на программируемых логических ИС АМ Сергиенко, ВИ Корнейчук Киев:«Корнійчук, 2005 | 7 | 2005 |
| Structured Design of Recursive Digital Filters YS Kanevskiy, LM Loginova, AM Sergiyenko Engineering Simulation 13, 381 - 390, 1996 | 7 | 1996 |
| VHDL generation of optimized IIR filters A Sergiyenko, A Serhienko 2019 IEEE 2nd Ukraine Conference on Electrical and Computer Engineering …, 2019 | 6 | 2019 |
| Nano-processor for the small tasks A Sergiyenko, O Molchanov, M Orlova 2019 IEEE 39th International Conference on Electronics and Nanotechnology …, 2019 | 6 | 2019 |
| Software/Hardware Co-design of the Microprocessor for the Serial Port Communications O Molchanov, A Orlova, Maria: Sergiyenko Advances in Computer Science for Engineering and Education II, ICCSEEA'2019 …, 2019 | 6 | 2019 |
VP simonenko ,В.П. Симоненко, Simo...професор информатикиПодтвержден адрес электронной почты в домене comsys.kpi.ua
