Michaela Blott
Michaela Blott
Xilinx Research
Подтвержден адрес электронной почты в домене xilinx.com
Finn: A framework for fast, scalable binarized neural network inference
Y Umuroglu, NJ Fraser, G Gambardella, M Blott, P Leong, M Jahre, ...
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
FINN-R An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
M Blott, TB Preußer, NJ Fraser, G Gambardella, K O’brien, Y Umuroglu, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-23, 2018
Achieving 10Gbps line-rate key-value stores with FPGAs
M Blott, K Karras, L Liu, K Vissers, J Bär, Z István
5th {USENIX} Workshop on Hot Topics in Cloud Computing (HotCloud 13), 2013
Syq: Learning symmetric quantization for efficient deep neural networks
J Faraone, N Fraser, M Blott, PHW Leong
Proceedings of the IEEE Conference on Computer Vision and Pattern …, 2018
A low-latency library in FPGA hardware for high-frequency trading (HFT)
JW Lockwood, A Gupte, N Mehta, M Blott, T English, K Vissers
2012 IEEE 20th annual symposium on high-performance interconnects, 9-16, 2012
OSNT: Open source network tester
G Antichi, M Shahbaz, Y Geng, N Zilberman, A Covington, M Bruyere, ...
IEEE Network 28 (5), 6-12, 2014
A flexible hash table design for 10gbps key-value stores on fpgas
Z István, G Alonso, M Blott, K Vissers
2013 23rd International Conference on Field programmable Logic and …, 2013
Scalable 10Gbps TCP/IP stack architecture for reconfigurable hardware
D Sidler, G Alonso, M Blott, K Karras, K Vissers, R Carley
2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015
Synetgy: Algorithm-hardware co-design for convnet accelerators on embedded fpgas
Y Yang, Q Huang, B Wu, T Zhang, L Ma, G Gambardella, M Blott, ...
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
FINN-L: Library extensions and design trade-off analysis for variable precision LSTM networks on FPGAs
V Rybalkin, A Pappalardo, MM Ghaffar, G Gambardella, N Wehn, M Blott
2018 28th international conference on field programmable logic and …, 2018
Scaling binarized neural networks on reconfigurable logic
NJ Fraser, Y Umuroglu, G Gambardella, M Blott, P Leong, M Jahre, ...
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and …, 2017
Dataflow architectures for 10gbps line-rate key-value-stores
M Blott, K Vissers
2013 IEEE Hot Chips 25 Symposium (HCS), 1-25, 2013
On how to improve fpga-based systems design productivity via sdaccel
G Guidi, E Reggiani, L Di Tucci, G Durelli, M Blott, MD Santambrogio
2016 IEEE international parallel and distributed processing symposium …, 2016
Architectural optimizations for high performance and energy efficient Smith-Waterman implementation on FPGAs using OpenCL
L Di Tucci, K O'Brien, M Blott, MD Santambrogio
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
Horizontal drill pipe racker and delivery system
VE Bolding, AJ Brooks III, MD Keen
US Patent 6,926,488, 2005
Scaling out to a single-node 80gbps memcached server with 40terabytes of memory
M Blott, L Liu, K Karras, K Vissers
7th {USENIX} Workshop on Hot Topics in Storage and File Systems (HotStorage 15), 2015
A hash table for line-rate data processing
Z István, G Alonso, M Blott, K Vissers
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 8 (2), 1-15, 2015
Inference of quantized neural networks on heterogeneous all-programmable devices
TB Preußer, G Gambardella, N Fraser, M Blott
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 833-838, 2018
FPGA research design platform fuels network advances
M Blott, J Ellithorpe, N McKeown, K Vissers, H Zeng
Xilinx Xcell Journal 4 (73), 24-29, 2010
Designing scalable FPGA architectures using high-level synthesis
J de Fine Licht, M Blott, T Hoefler
Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of …, 2018
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