Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks K Kim, J Kim, J Yu, J Seo, J Lee, K Choi Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 231 | 2016 |
A new stochastic computing multiplier with application to deep convolutional neural networks H Sim, J Lee Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 157 | 2017 |
Efficient FPGA acceleration of convolutional neural networks using logical-3D compute array A Rahman, J Lee, K Choi 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 129 | 2016 |
Compilation approach for coarse-grained reconfigurable architectures J Lee, K Choi, ND Dutt IEEE Design & Test of Computers 20 (1), 26-33, 2003 | 120 | 2003 |
Efficient instruction encoding for automatic instruction set design of configurable ASIPs J Lee, K Choi, N Dutt Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 84 | 2002 |
An algorithm for mapping loops onto coarse-grained reconfigurable architectures J Lee, K Choi, ND Dutt ACM Sigplan Notices 38 (7), 183-188, 2003 | 74 | 2003 |
An energy-efficient random number generator for stochastic circuits K Kim, J Lee, K Choi 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 256-261, 2016 | 68 | 2016 |
Double MAC: Doubling the performance of convolutional neural networks on modern FPGAs D Nguyen, D Kim, J Lee Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 65 | 2017 |
Reconfigurable ALU array architecture with conditional execution J Lee, Y Kim, J Jung, S Kang, K Choi International Soc. Design Conference (ISOOC)[online] Oct 25, 2004 | 64 | 2004 |
Accurate and efficient stochastic computing hardware for convolutional neural networks J Yu, K Kim, J Lee, K Choi 2017 IEEE International Conference on Computer Design (ICCD), 105-112, 2017 | 62 | 2017 |
Approximate de-randomizer for stochastic circuits K Kim, J Lee, K Choi 2015 International SoC Design Conference (ISOCC), 123-124, 2015 | 62 | 2015 |
Scalable stochastic-computing accelerator for convolutional neural networks H Sim, D Nguyen, J Lee, K Choi 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 696-701, 2017 | 52 | 2017 |
Design space exploration of FPGA accelerators for convolutional neural networks A Rahman, S Oh, J Lee, K Choi Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 51 | 2017 |
A software solution for dynamic stack management on scratch pad memory A Kannan, A Shrivastava, A Pabalkar, J Lee 2009 Asia and South Pacific Design Automation Conference, 612-617, 2009 | 50 | 2009 |
SDRM: Simultaneous determination of regions and function-to-region mapping for scratchpad memories A Pabalkar, A Shrivastava, A Kannan, J Lee High Performance Computing-HiPC 2008: 15th International Conference …, 2008 | 49 | 2008 |
Improving performance of nested loops on reconfigurable array processors Y Kim, J Lee, TX Mai, Y Paek ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-23, 2012 | 45 | 2012 |
High throughput data mapping for coarse-grained reconfigurable architectures Y Kim, J Lee, A Shrivastava, JW Yoon, D Cho, Y Paek IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 41 | 2011 |
A compiler optimization to reduce soft errors in register files J Lee, A Shrivastava ACM Sigplan Notices 44 (7), 41-49, 2009 | 41 | 2009 |
Static analysis to mitigate soft errors in register files J Lee, A Shrivastava 2009 Design, Automation & Test in Europe Conference & Exhibition, 1367-1372, 2009 | 39 | 2009 |
Flattening-based mapping of imperfect loop nests for CGRAs J Lee, S Seo, H Lee, HU Sim Proceedings of the 2014 International Conference on Hardware/Software …, 2014 | 37 | 2014 |