Method of forming a multi-layer semiconductor structure incorporating a processing handle member R Reif, KN Chen, CS Tan, A Fan
US Patent 7,307,003, 2007
242 2007 Wafer-level bonding/stacking technology for 3D integration CT Ko, KN Chen
Microelectronics reliability 50 (4), 481-488, 2010
233 2010 Wafer-level 3D integration technology SJ Koester, AM Young, RR Yu, S Purushothaman, KN Chen, ...
IBM Journal of Research and Development 52 (6), 583-597, 2008
229 2008 Technology, performance, and computer-aided design of three-dimensional integrated circuits S Das, A Fan, KN Chen, CS Tan, N Checka, R Reif
Proceedings of the 2004 international symposium on Physical design, 108-115, 2004
208 2004 Morphology and bond strength of copper wafer bonding KN Chen, CS Tan, A Fan, R Reif
Electrochemical and Solid-State Letters 7 (1), G14, 2003
190 2003 Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces of nanotwinned Cu CM Liu, HW Lin, YS Huang, YC Chu, C Chen, DR Lyu, KN Chen, KN Tu
Scientific reports 5 (1), 9734, 2015
188 2015 Low temperature bonding technology for 3D integration CT Ko, KN Chen
Microelectronics reliability 52 (2), 302-311, 2012
172 2012 Fabrication technologies for three-dimensional integrated circuits R Reif, A Fan, KN Chen, S Das
Proceedings International Symposium on Quality Electronic Design, 33-37, 2002
168 2002 Three-dimensional integrated circuit (3D IC) key technology: Through-silicon via (TSV) WW Shen, KN Chen
Nanoscale research letters 12, 1-9, 2017
162 2017 Evidence for segregation of Te in Ge2Sb2Te5 films: Effect on the “phase-change” stress L Krusin-Elbaum, C Cabral, KN Chen, M Copel, DW Abraham, KB Reuter, ...
Applied physics letters 90 (14), 2007
137 2007 Wafer-level Cu–Cu bonding technology YS Tang, YJ Chang, KN Chen
Microelectronics Reliability 52 (2), 312-320, 2012
136 2012 A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding F Liu, RR Yu, AM Young, JP Doyle, X Wang, L Shi, KN Chen, X Li, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
130 2008 Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators PY Hsieh, YJ Chang, PJ Chen, CL Chen, CC Yang, PT Huang, YJ Chen, ...
2019 IEEE International Electron Devices Meeting (IEDM), 3.1. 1-3.1. 4, 2019
125 2019 Microstructure evolution and abnormal grain growth during copper wafer bonding KN Chen, A Fan, CS Tan, R Reif, CY Wen
Applied Physics Letters 81 (20), 3774-3776, 2002
122 2002 Low-temperature direct copper-to-copper bonding enabled by creep on highly (1 1 1)-oriented Cu surfaces CM Liu, H Lin, YC Chu, C Chen, DR Lyu, KN Chen, KN Tu
Scripta Materialia 78, 65-68, 2014
107 2014 Wafer-to-wafer alignment for three-dimensional integration: A review SH Lee, KN Chen, JJQ Lu
Journal of Microelectromechanical Systems 20 (4), 885-898, 2011
104 2011 Irreversible modification of Ge2Sb2Te5 phase change material by nanometer-thin Ti adhesion layers in a device-compatible stack C Cabral, KN Chen, L Krusin-Elbaum, V Deline
Applied physics letters 90 (5), 2007
99 2007 Microstructure examination of copper wafer bonding KN Chen, A Fan, R Reif
Journal of Electronic Materials 30, 331-335, 2001
97 2001 Novel Cu-to-Cu Bonding With Ti Passivation at 180 in 3-D Integration YP Huang, YS Chien, RN Tzeng, MS Shy, TH Lin, KH Chen, CT Chiu, ...
IEEE Electron Device Letters 34 (12), 1551-1553, 2013
96 2013 Copper bonded layers analysis and effects of copper surface conditions on bonding quality for three-dimensional integration KN Chen, CS Tan, A Fan, R Reif
Journal of Electronic Materials 34, 1464-1467, 2005
92 2005