Armin Tajalli
Title
Cited by
Cited by
Year
Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes
H Cronie, A Shokrollahi, A Tajalli
US Patent 8,649,445, 2014
1402014
Subthreshold source-coupled logic circuits for ultra-low-power applications
A Tajalli, EJ Brauer, Y Leblebici, E Vittoz
IEEE Journal of Solid-State Circuits 43 (7), 1699-1710, 2008
1352008
Efficient processing and detection of balanced codes
A Tajalli, H Cronie, A Shokrollahi
US Patent 8,593,305, 2013
1132013
Implementing ultra-high-value floating tunable CMOS resistors
A Tajalli, Y Leblebici, EJ Brauer
Electronics letters 44 (5), 349-350, 2008
1022008
Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes
H Cronie, A Shokrollahi, A Tajalli
US Patent 9,154,252, 2015
662015
Extreme low-power mixed signal IC design: subthreshold source-coupled circuits
A Tajalli, Y Leblebici
Springer Science & Business Media, 2010
652010
Symmetric is linear equalization circuit with increased gain
A Tajalli
US Patent 9,148,087, 2015
632015
Design trade-offs in ultra-low-power digital nanoscale CMOS
A Tajalli, Y Leblebici
IEEE Transactions on Circuits and Systems I: Regular Papers 58 (9), 2189-2200, 2011
602011
A Slew Controlled LVDS Output Driver Circuit in 0.18 m CMOS Technology
A Tajalli, Y Leblebici
IEEE journal of solid-state circuits 44 (2), 538-548, 2009
562009
High performance phase locked loop
A Tajalli
US Patent 10,057,049, 2018
492018
Vector signaling codes for densely-routed wire groups
A Shokrollahi, A Hormati, A Tajalli
US Patent 10,333,741, 2019
452019
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept
A Tajalli, E Vittoz, Y Leblebici, EJ Brauer
ESSCIRC 2007-33rd European Solid-State Circuits Conference, 304-307, 2007
372007
Ultra-low power subthreshold current-mode logic utilising PMOS load device
A Tajalli, E Vittoz, Y Leblebici, EJ Brauer
Electronics Letters 43 (17), 911-913, 2007
342007
Leakage current reduction using subthreshold source-coupled logic
A Tajalli, Y Leblebici
IEEE Transactions on Circuits and Systems II: Express Briefs 56 (5), 374-378, 2009
322009
Improving power-delay performance of ultra-low-power subthreshold SCL circuits
A Tajalli, M Alioto, Y Leblebici
IEEE Transactions on Circuits and Systems II: Express Briefs 56 (2), 127-131, 2009
282009
10.1 A pin-efficient 20.83 Gb/s/wire 0.94 pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS
A Shokrollahi, D Carnelli, J Fox, K Hofstra, B Holden, A Hormati, P Hunt, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 182-183, 2016
272016
A Power-Efficient Clock and Data Recovery Circuit in 0.18 CMOS Technology for Multi-Channel Short-Haul Optical Data Communication
A Tajalli, P Muller, Y Leblebici
IEEE journal of solid-state circuits 42 (10), 2235-2244, 2007
232007
Method of using a rule based script to describe gaming machine payout
DR Nelson, DM Oles, SG LeMay, B Webb
US Patent 7,104,889, 2006
23*2006
Low-power and widely tunable linearized biquadratic low-pass transconductor-C filter
A Tajalli, Y Leblebici
IEEE Transactions on Circuits and Systems II: Express Briefs 58 (3), 159-163, 2011
222011
An analysis of the initiation of upward flashes from tall towers with particular reference to Gaisberg and Säntis Towers
A Smorgonskiy, A Tajalli, F Rachidi, M Rubinstein, G Diendorfer, H Pichler
Journal of Atmospheric and Solar-Terrestrial Physics 136, 46-51, 2015
212015
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