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Ziaul Choudhury
Ziaul Choudhury
Senior Software Engineer 2 at AMD
Verified email at amd.com
Title
Cited by
Cited by
Year
FPGA accelerator for stereo vision using semi-global matching through dependency relaxation
S Shrivastava, Z Choudhury, S Khandelwal, S Purini
2020 30th International Conference on Field-Programmable Logic and …, 2020
122020
An FPGA overlay for CNN inference with fine-grained flexible parallelism
Z Choudhury, S Shrivastava, L Ramapantulu, S Purini
ACM Transactions on Architecture and Code Optimization (TACO) 19 (3), 1-26, 2022
82022
Accelerating local laplacian filters on fpgas
S Khandelwal, Z Choudhury, S Shrivastava, S Purini
2020 30th International Conference on Field-Programmable Logic and …, 2020
42020
Bitwidth customization in image processing pipelines using interval analysis and SMT solvers
S Purini, V Benara, Z Choudhury, U Bondhugula
Proceedings of the 29th international conference on compiler construction …, 2020
42020
A randomized cryptographic algorithm and its simulation in C and MATLAB with its hardware implementation in Verilog HDL
S Dev, ZH Choudhury
2009 3rd International Conference on Anti-counterfeiting, Security, and …, 2009
42009
A hybrid CPU+ GPU working-set dictionary
Z Choudhury, S Purini, SR Krishna
2016 15th International Symposium on Parallel and Distributed Computing …, 2016
32016
An efficient heap management technique with minimum fragmentation and auto compaction
KL Baishnab, S Dev, ZH Choudhury
2010 3rd International Conference on Computer Science and Information …, 2010
22010
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler
Z Choudhury, A Gulati, S Purini
ACM Transactions on Architecture and Code Optimization 20 (4), 1-25, 2023
12023
Accelerating LU-decomposition of arbitrarily sized matrices on FPGAs
MK Kumar, Z Choudry, S Purini
2023 International VLSI Symposium on Technology, Systems and Applications …, 2023
12023
A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra
B George, OJ Omer, Z Choudhury, A V, S Subramoney
ACM Transactions on Embedded Computing Systems (TECS) 21 (5), 1-30, 2022
12022
Synthesizing power and area efficient image processing pipelines on fpgas using customized bit-widths
V Benara, Z Choudhury, S Purini, U Bondhugula
arXiv preprint arXiv:1803.02660, 2018
12018
Heterogeneous (CPU+ GPU) working-set hash tables
Z Choudhury, S Purini
Proceedings of the 9th International Workshop on Programmability and …, 2016
12016
Accuracy Configurable FPGA Implementation of Harris Corner Detection
S Maurya, Z Choudhury, S Purini
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 422-427, 2022
2022
Automatic Bitwidth Customization for Image Processing Pipelines on FPGAs through a DSL Compiler
V BENARA, Z CHOUDHURY, S PURINI, U BONDHUGULA
arXiv preprint arXiv: 1803.02660, 2018
2018
High Performance Self Organizing Dynamic Dictionaries
Z Choudhury
International Institute of Information Technology Hyderabad, 2016
2016
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